The complexity of integrated circuits forced designers to use various testing procedures and architectures.
During the last couple of years a group of companies developed what is now known as the IEEE P1500 scalable architecture for testing embedded cores. In a nutshell, the P1500 defines an integrated circuit architecture that is based upon wrappers that wrap cores (these re-usable cores are also referred to as Intellectual Property). The development of the P1500 was intended to ease the testing procedures of multiple core integrated circuits and simplify the re-use of previously developed cores.
Various patents and patent applications, all being incorporated herein by reference, describe devices and method for testing components using wrappers. Some of the mentioned patents and patent applications describe P1500 compliant architectures: U.S. patent application publication serial number 2005/0204236A1 of Whetsel, U.S. patent application publication serial number 2004/0187058A1 of Yamada et al., U.S. patent application publication serial number 2005/0283690 of McLaurin; U.S. Pat. No. 6,701,476 of Pouya et al., U.S. patent application publication serial number 2003/0120986A1 of Whestel; and PCT patent application publication serial number WO2005/088325 of Goel.
The following two articles, also being incorporated herein by reference, also describe P1500 compliant wrappers: “Design of reconfigurable access wrappers for embedded core based SOC test”, S. Kpranne, Proceedings of the international symposium on quality electronic design (ISQED' 02), 2002 IEEE; and “IEEE P1500-compliant test wrapper design for hierarchical cores”, A. Sehgal, S. K. Goel, E. J. Marinissen, K. Chakrabarty, ICT international test conference, 2004 IEEE.
FIG. 1 illustrates a prior art P1500 compliant integrated circuit 8. For simplicity of explanation FIG. 1 illustrates only a single core 9, but those of skill in the art will appreciate that a P1500 compliant integrated circuit usually includes multiple cores that can be arranged in a hierarchical manner.
Integrated circuit 8 includes core 9 that is wrapped by wrapper 11. Core 9 has many core pins. Each core pin is connected to one wrapper cell. It is noted that two wrapper cells can be required per core pin if the wrapper is required to enable at speed testing of core 9.
The wrapper cells 12 are also connected to each other in order to form a wrapper boundary register. In addition, wrapper 11 includes a wrapper serial input 12, a wrapper serial output (WSO) 13, a wrapper instruction register (WIR) 17, a wrapper bypass register 15, and test access mechanism (TAM) 16 that is connected to wrapper 11.
Many modern cores include a large number of pins. Allocating one or even two wrapper cells per each core pin is area consuming, as well as complicates the design of the wrapper.
There is a need to provide an efficient wrapper, efficient method for designing wrappers and an efficient method for testing devices.